1. Field of the Invention
The present invention relates to an encryption processing circuit and an encryption processing method.
2. Description of the Related Art
Conventionally, encryption processing techniques for protecting secret information have been widely used. Also, the encryption processing technique may be realized by hardware.
For example, when the nonlinear conversion processing in the S-Box of DES (Data Encryption Standard) which is one of the encryption schemes is realized by hardware, the processing circuit is realized by using a memory such as a ROM or by combining various circuits. Note that the processing in the S-Box is processing for converting input data into another data in one-to-one correspondence.
On the other hand, as one of the encryption analysis techniques, there is a technique referred to as power analysis for stealing secret data by observing the power consumption in hardware which performs encryption processing. When secret data is correlated with electric power consumed in a hardware circuit at the time of processing secret data, the secret data used in encryption processing may be stolen by a so-called power analysis attack using the technique. Therefore, in recent years, as disclosed, for example, in Japanese Patent Laid-Open No. 2005-31471, there have been proposed various techniques relating to measures against the power analysis attack.
When an encryption processing circuit is configured by a combinational circuit, the combinational circuit is generally generated in many cases by using a technique, such as automatic logic synthesis processing.
However, when the automatic logic synthesis processing technique is used, it is difficult to predict what circuit is generated, and it is also difficult to improve the synthesized circuit in many cases. Therefore, it is not possible to eliminate the possibility that in the generated combinational circuit, the power consumption at the time of processing secret data is correlated with the secret data. Even if such correlation exists, it is difficult to eliminate the correlation by improving the circuit.
Note that, as disclosed, for example, in Japanese Patent Laid-Open No. 2003-223100, there is proposed a technique capable of improving the circuit generated by the automatic logic synthesis processing. However, the technique has a problem that the circuit scale is enlarged.